`timescale 1ns/10ps
`define clock_period 20

module arithmetic_tb;

	reg[7:0] a;
	reg[7:0] b;
	reg clk_50M;
	reg select;
	
	wire[7:0] c;
	wire[7:0] d;

	arithmetic arithmetic0(
		.Clk_50M(clk_50M),
		.Select(select),
		.A(a),
		.B(b),
		.C(c),
		.D(d)
	);
	
	always #(`clock_period / 2) clk_50M = ~clk_50M;
	
	initial begin
		//时钟初始化
		clk_50M = 1'b0;
		
		//第一次计算
		a = 8'd20;
		b = 8'd3;
		select = 1'b1;//先除法
		#(`clock_period);
		select = 1'b0;//再取模
		#(`clock_period);
		
		//第二次计算
		a = 8'd13;
		b = 8'd5;
		select = 1'b1;//先除法
		#(`clock_period);
		select = 1'b0;//再取模
		#(`clock_period);
		
		$stop;
	end
endmodule
		